This paper describes a novel way to exploit the computation capabilities delivered by modern Field-Programmable Gate Arrays\n(FPGAs), not only towards a higher performance, but also towards an improved reliability. Computation-specific pieces of circuitry\nare dynamically scheduled and allocated to different resources on the chip based on a set of novel algorithms which are described\nin detail in this article. These algorithms consider most of the technological constraints existing inmodern partially reconfigurable\nFPGAs as well as spontaneously occurring faults and emerging permanent damage in the silicon substrate of the chip. In addition,\nthe algorithms target other important aspects such as communications and synchronization among the different computations that\nare carried out, either concurrently or at different times. The effectiveness of the proposed algorithms is tested by means of a wide\nrange of synthetic simulations, and, notably, a proof-of-concept implementation of them using real FPGA hardware is outlined.
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